The present invention relates generally to design automation, and relates more particularly to timing analysis for testing of integrated circuit (IC) chips.
When IC chips come off the manufacturing line, the chips are tested “at-speed” to ensure that they perform correctly (and to filter out chips that do not perform correctly). In particular, a set of paths is selected, and the set of paths is then tested for each chip in order to identify the chips in which one or more of the selected paths fail timing requirements. Parametric process variation delay defects that affect multiple cell and wire delays are among the most difficult defects to test.
One way to detect process variation delay defects is through statistical testing, which relies on parameterized statistical timing information provided by a statistical timing analysis engine. However, many chips are designed using deterministic timing. In this case, the correctness of the chip design is verified using static timing analysis of the chip at several process corners. The deterministic timing data used here is not provided in a format that is compatible with more advanced statistical testing methodologies. Therefore, the existing deterministic design and test methodologies cannot use statistical testing methods for detecting process variation defects.